eCACTI: An Enhanced Power Estimation Model for On-chip Caches

There is a growing need for accurate power models at the higher levels of design hierarchy. CACTI is a micro-architecture level tool widely used (i) to estimate power dissipation in caches and (ii) to determine the cache configuration that best meets the desired optimization criterion. However, we observed several limitations in CACTI that lead to inaccuracies in cache power estimates especially as we move to deep sub-micron (DSM) technologies: a) lack of models to account for leakage power, b) use of constant gate widths for most devices irrespective of its capacitive load, and c) lack of models to account for power dissipation in sub-blocks that are outside the time critical path. As a result, the cache configuration determined by CACTI may not be optimal because of these limitations. In this paper, we describe eCACTI (enhanced CACTI), a tool that addresses these limitations in CACTI thereby improving the accuracy of its power estimates. We validated eCACTI power estimates against SPICE based simulations on industrial designs. Furthermore, we show that for DSM technologies, CACTI does not generate power optimal cache configuration, which highlights the need for the enhancements we developed in eCACTI. Finally, we demonstrate the use of eCACTI to study the effects of (i) technology on cache leakage and total cache power, (ii) dual-Vth optimization on sub-block and total cache leakage power, (iii) effects of varying cache size, block size, and associativity for DSM technologies.